Laminated Busbar Design Guide

In a typical power-electronics build, the same power-electronics laminated busbar carries the DC link between the buffer capacitors and the IGBT or SiC power modules — forward and return paths on adjacent planes, with terminals lined up exactly where the modules and capacitors sit. Electrically it is a multilayer circuit; mechanically it is a single rigid part that installs in one motion.

Because the conductor geometry is tooled rather than hand-routed, the same assembly ships consistent unit to unit: the same loop area, the same terminal positions, the same insulation margins. That repeatability is what makes the part viable at production volumes — the geometry behind it is detailed in our low-inductance busbar design article.

We build from C11000 copper as standard; aluminum conductors are available on request when weight or raw-material cost drives the selection. The trade-offs are detailed in copper vs aluminum busbar conductors. Every lot passes in-house QC under our laminated busbar testing process — hipot, insulation resistance, dimensional, visual and continuity checks — with batch test records and CoC-style documentation supplied on request.

Layer count typically runs from one to six or more. Adjacent conductors are offset in the stack so every terminal stays reachable, and the dielectric covers the copper with a margin matched to the voltage class. After lamination, cut edges are sealed before terminals are welded or fastened, so the finished part can be handled like any other component.

Three indices decide the choice beyond cost and thickness:

• Relative Temperature Index (RTI), defined per the UL 746 method: the continuous-use temperature at which a key property retains half its initial value after 20,000 hours. Standard PET sits near 105 °C; high-temperature film systems run to 130 °C and above. Insulation lifetime follows the Arrhenius pattern — roughly every 10 °C rise halves the remaining life.
• Comparative Tracking Index (CTI): a measure of surface tracking risk under pollution. It sets the creepage distance between free terminals and matters most above 1000 V. A good-CTI film such as PET can roughly halve the required creepage compared with a lower-CTI alternative.
• Flammability: film plus adhesive plus conductor is qualified as a composite, typically to UL 94 V-0 class in standard constructions.

Above roughly 1000 V, flexible film alone is usually not enough. A rigid inter-layer board — commonly glass-reinforced polyester — is added between conductor sub-assemblies, with a rule of thumb of about 1 mm of rigid insulation per kV of maximum operating voltage. The related field-stress design and acceptance testing are covered in partial discharge in laminated busbars, and temperature-limited designs are covered in busbar thermal management.

Two limits govern the sizing, and they are easy to confuse. Temperature rise: resistive heating in the conductor must stay within the margin your enclosure allows — the 30 °C reference above assumes a 40 °C ambient and free-air mounting. Insulation class: the dielectric sets the ceiling — a 105 °C PET system cannot run at 130 °C no matter how large the copper is. Sizing runs both ways: first the cross-section for temperature rise, then the dielectric choice against the resulting steady-state temperature.

Doubling the copper area does not double the rating inside an enclosure — adjacent layers and neighboring parts heat each other, and the derating factors in our ampacity chart apply on top of these numbers.

Every switching circuit pays a voltage tax for its loop inductance. When a switch commutates from on to off, the loop current cannot stop instantly; it crashes into the now-open switch and creates a spike across the device. The spike follows V = L × di/dt — loop inductance multiplied by the rate of current change. The faster the switch, SiC devices in particular, the more expensive millihenry-scale loop inductance becomes.

Inductance is set by the magnetic flux between the forward and return paths, and flux is proportional to loop area. In a cable harness the positive and negative conductors sit centimeters apart and the loop area is large. In a laminated busbar they sit fractions of a millimeter apart as parallel planes — the geometry that naturally cancels flux. As a reference, for an equivalent 1 m run: a pair of round wires 1 mm apart carries roughly 0.4 mH of loop inductance; the same cross-section laminated as a stack lands near 50 nH, and with thin-film dielectrics under 0.2 mm the same loop can fall below 20 nH.

Two empirical scaling rules from reference design practice are worth memorizing:

• Doubling the length of the commutating loop adds roughly 30% to its stray inductance.
• Doubling the insulation thickness between the opposing planes adds roughly 80%. Layer spacing matters more than loop length.

The design consequence is a balancing act: minimize spacing while still meeting the required insulation level, minimize loop length while still leaving room for heat, and balance positive and negative plane overlap at every terminal. Terminal overlap — not the straight run of bar — usually dominates the final number. We cover the full rule set, including FEM-based iteration, in low-inductance busbar design: principles and layout rules.

Small geometry changes move the number a lot, so the practical workflow is simulation, not trial prototypes: model the busbar alone, replace the capacitors with a short-circuit block so current follows the lowest-impedance path, probe at the device terminals, and iterate on the highest-flux areas. A reference optimization loop runs from about 12 nH on a baseline bent-terminal layout to below 5 nH after flattening terminals and increasing plane overlap — roughly a 60% reduction, with the terminal overlap and the capacitor interface responsible for most of the gain.

A cut copper edge is where insulation failure usually starts. Two failure modes meet at the edge: tracking along the surface under voltage, and partial discharge inside any trapped air gap.

Edge sealing. The dielectric film is coated with an adhesive that activates during the heat-and-pressure lamination cycle. It bonds the film to the conductor and, critically, folds over the cut edge so that no bare edge and no air gap is left exposed. The seal has to hold across the full atmospheric range of the design — humidity cycling and, at altitude, low pressure, where the breakdown strength of any trapped air bubble falls sharply (air dielectric strength drops from roughly 3.1 kV/mm at sea level to about 2.0 kV/mm near 0.5 bar).

Creepage and clearance. Clearance is the air distance between two conductors; creepage is the surface distance along the insulation between free terminals. Requirements scale with voltage class and pollution severity, and IEC 60664-style tables are the usual starting reference. The film's CTI rating sets how much creepage you actually need — which is why we confirm voltage class and environment before recommending a dielectric system.

Partial discharge. Even a sealed stack can host micro-gaps, and air in a micro-gap ionizes under field stress. Per the IEC 60270 definition (clause 3.1), partial discharge is a localized discharge that only partially bridges the insulation — typically pulses shorter than 1 µs. Intermittent PD is harmless; continuous PD above 10 pC erodes insulation over years and can end in short circuit. We verify PD below 10 pC on finished parts, even at test voltages above the operating voltage. Full mechanism and test guidance: partial discharge in laminated busbars.

The required level of edge sealing and creepage scales with the environment, not just the voltage:

Terminals are where current enters and leaves the stack, and where most field problems originate. The standard options:

Four connection techniques come up repeatedly in DFM review:

• Busbar to power module: studs or tabs should mirror the module terminal pattern with minimum open-loop gap; offset or angled terminals add inductance quickly.
• Capacitor to busbar: bolting or soldering DC-link capacitors directly onto the busbar planes removes long individual leads — the single largest inductance reduction available in a DC-link design.
• Busbar to cable: integrated connectors let cabinet wiring plug into the stack without a transition block.
• Busbar to busbar: bolted joints are standard; where the two joined devices move relative to each other — tolerance stack-up, thermal expansion — a flexible lamella stack between rigid ends solves the problem. See flexible laminated busbars.

Joint contact resistance is kept low by tin plating the conductor, standard on our parts, which also protects against oxidation over the product life.

• Confirm the voltage class — this sets dielectric selection and creepage distances.
• State continuous AND peak current — cross-section is sized against both.
• Define terminal types and pitch — studs, blade tabs, welded, fused links.
• Check edge distances and dielectric clearances with your assembly process.
• Consider thermal cycling, vibration and your enclosure ambient.
• Send the drawing to us for our busbar DFM review service before tooling.

Beyond the items above, our DFM review typically turns up four additional things to confirm early:

• Terminal torque values, and whether the joint sees thermal cycling — which decides washer selection.
• Clearance above and below the stack inside the enclosure; anything close by changes the cooling budget.
• Whether DC-link capacitors mount directly on the busbar, which affects plane overlap and terminal layout.
• The mission profile — the percentage of run time spent at each temperature — because insulation lifetime is set by average thermal state, not peak temperature.